Design and Implementation of USB 3.0 Communication Architecture Based on FPGA

doi:10.3969/j.issn.1006-2475.2017.10.024

Abstract

Abstract: In order to solve the problem of bandwidth bottleneck in the communication between USB and host, a high speed communication architecture based on USB3.0 protocol is designed to provide an alternative scheme for USB data communication between embedded devices and PC. This design uses the EZ-USB FX3 chip of Cypress as a USB peripheral controller, FPGA as the main control chip in the hardware system. Through the design of FPGA hardware system, design and optimization of device firmware, the architecture supports USB 2.0/3.0 adaptive interfaces, it can realize the variable frame length communication between host and domestic embedded CPU and SRAM, hardware transmission speed of 360 MB/s, continuous data transmission speeds of up to 148 MB/s.

Key words: USB 3.0, FPGA, multi-interface, high speed, FSM controller

WU Chun-chun, HU Huai-xiang, JIN Da, CHEN Xiang-yu. Design and Implementation of USB 3.0 Communication Architecture Based on FPGA[J]. Computer and Modernization, doi: 10.3969/j.issn.1006-2475.2017.10.024.

References

［1］ Axelson J. USB开发大全［M］. 4版. 李鸿鹏，郑瑞霞，陈香凝，等译. 北京：人民邮电出版社， 2011.

［2］褚振勇,翁木云，高楷娟. FPGA设计及应用［M］. 3版. 西安：西安电子科技大学出版社， 2012.

［3］杨翠翠，朱向东，李帆. 基于USB3.0协议的PC与FPGA通信系统的设计［J］. 电子科技， 2014(10):136-138. 

［4］黄义,翟国芳,万旻，等. 基于Cy7c67300 USB控制器和FPGA的USB接口传输系统［J］. 电子测量技术, 2014,37(2):78-81.

［5］曾志斌，袁雨舟，姚引娣. 一种FPGA高速访问USB设备的设计方案［J］. 单片机与嵌入式系统应用， 2014（8）：46-48.

［6］余芳. FPGA与PC机USB通信的实现［D］. 哈尔滨:哈尔滨工业大学， 2010.

［7］徐文波，田耘. Xilinx FPGA开发实用教程［M］. 2版. 北京：清华大学出版社， 2012.

［8］ Cypress Semiconductor Corporation． Getting Started with EZ-USB FX3.0［EB/OL］. http://www.cypress.com/documentation/application-notes/an75705-getting-started-ez-usbr-fx3tm-zh, 2017-05-05.

［9］ Cypress Semiconductor Corporation． Designing with the EZ-USB FX3 Slave FIFO Interface［EB/OL］. http://www.cypress.com/documentation/application-notes/an65974-desi-gning-ez-usb-fx3-slave-fifo-interface, 2017-07-18.

［10］Cypress Semiconductor Corporation． Optimizing USB 3.0 Throughput with EZ-USB FX3［EB/OL］. http://www.cypress.〖KG-*2〗com/documentation/application-notes/an86947-optim-izing-usb-30-throughput-ez-usb-fx3, 2017-09-16. 

［11］杨志坤,曾博,汤国文. 基于FPGA的嵌入式系统USB接口设计［J］．电子设计工程， 2010，18(1):30-31.

［12］夏宇闻. Verilog数字系统设计教程［M］. 3版. 北京:北京航空航天大学出版社, 2015.

［13］张世伟，印世平，何运桃. USB2.0 接口传输的FPGA控制与实现［J］. 国外电子测量技术, 2009,28(11):74-76. 

［14］袁卫,张冬阳. 基于Verilog的FPGA与USB2.0高速接口设计［J］. 现代电子技术, 2009(1):161-163.

［15］王水鱼，陈璐. 基于FPGA和USB的数据采集系统的设计［J］. 微型机与应用, 2010,29(22):19-21.

［16］ Jolfaei F A, Mohammadizadeh N, Sadri M S, et al. High speed USB 2.0 interface for FPGA based embedded systems［C］// Proceedings of the 2009 4th International Conference on Embedded and Multimedia Computing. 2009:1-6. 

［17］徐超，刘冲，王永纲. 基于FPGA和USB2.0协议的通用数据传输设计［J］. 微型机与应用, 2016,35(16):41-43. 

［18］Linares-Barranco A， Gomez-Rodriguez F， Villanueva V， et al. A USB3.0 FPGA event-based filtering and tracking framework for dynamic vision sensors［C］// IEEE International Symposium on Circuits & Systems. 2015:2417-2420.

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