Abstract: The paper introduces the use of System Generator of Xilinx that is system level modeling tool in the MATLAB/Simulink environment for the completion of algorithm modeling of the UART procedure, generates the corresponding code to the FPGA, and realizes the function between UART communication data sending and receiving. Experiment results show that the System Generator as a system level modeling tool is not only to eliminate the gap between the original system engineers and hardware and software engineers, but also to simplify the traditional development process of the FPGA.

Key words: UART, FPGA, System Generator