A Summarization of Dynamic Partial Reconfiguration Based on FPGA

doi:10.3969/j.issn.1006-2475.2014.03.049

Abstract

Abstract: The reconfigurable computing is a new computing architecture, which combines the advantages of general purpose processor and application specific integrated circuit. It is of flexibility and high-performance. The dynamic partial reconfiguration of FPGA allows on-the-fly dynamic reconfiguration of part of the logic resources in FPGA to finish the function transformation. Therefore, it can improve the integrations and flexibility and the tolerance of error of the system. Additionally, it can reduce the cost and the power consumption of the system. This paper presents the theory of dynamic partial reconfiguration of FPGA. Then the paper introduces the implementations of dynamic reconfiguration and analyzes four kinds of the most common ways in details. It also presents the latest development and applications of dynamic partial reconfiguration. At last the future work and study directions of dynamic partial reconfiguration of FPGA are presented.
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Key words: reconfigurable computing, FPGA dynamic partial reconfiguration, EAPR

CLC Number:

TP311.52

ZHANG Yu1，FAN Jian-hua2, LYU Zun-ming2, WANG Tong-xiang1. A Summarization of Dynamic Partial Reconfiguration Based on FPGA[J]. Computer and Modernization, doi: 10.3969/j.issn.1006-2475.2014.03.049.

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