关键词: 信息系统, AES算法, 功能仿真, 物理设计

Abstract: In order to ensure the security of information systems, an ASIC implemention of AES based on Chartered 0.35um CMOS process technology is shown. The Verilog HDL of AES algorithm is developed after the architecture design and module partition. The function simulation results demonstrate that the design works well. Finally, the physical design of the cipher chip is completed by Astro.

Key words: information system, AES algorithm, function simulation, physical design