参考文献:
[1]Estrin G, Bussell B, Turn R, et al. Parallel processing in a restructurable computer system[J]. IEEE Transaction on Electronic Computers, 1963,12(6):747-755.
[2]Hauser J R, Wawrzynek J.Garp: A MIPS processor with a reconfigurable coprocessor[C]// IEEE Symposium on Field Programmable Custom Computing Machines. 1997:12-21.
[3]Ethen Mirsky, Andre DeHon. MATRIX:A reconfigurable computing architecture with configurable instruction distribution and deployable resources[C]// IEEE Symposium on FPGAs for Custom Computing Machines. 1996:157-166.
[4]Xilinx Corp. Partial Reconfiguration of Xilinx FPGAs Using ISE Design Suite[DB/OL]. http://www.xilinx.com/support/documentation/white_papers/wp374.Partial.Reconfig_Xilinx_FPGAs.pdf, 2012-05-30.
[5]Guccione S, Levi D, Sundararajan P. JBits: Javabased interface for reconfigurable computing[C]// The 2nd Annual Military and Aerospace Applications of Programmable Devices and Technologies Conference (MAPLD). 1999:261.
[6]Anup Kumar Raghavan, Peter Sutton. JPG: A partial bitstream generation tool to support partial reconfiguration in irtex FPGAs[C]// Proceedings of the 16th International Parallel and Distributed Processing Symposium. 2002:155-160.
[7]Neil Steiner, Aaron Wood, Hamid Shojaei, et al. Torc: Towards an opensource tool flow[C]// Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays. 2011:41-44.
[8]Xilinx Corp. DifferenceBased Partial Reconfiguration[DB/OL]. http://www.xilinx.com/support/documeatation/application_notes/xapp290.pdf, 2007-12-03.
[9]Xilinx Corp. Early Access Partial Reconfiguration User Guide[DB/OL]. http://www.xilinx.com/support/documeatation/sw_manuals/xilinx14_1/Plan Ahead_User Guide.pdf, 2012-04-24.
[10]Abbott A L, Athanas P M, Chen L, et al. Finding lines and building pyramids with SPLSSH2[C]// Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines. 1994:155-163.
[11]Mubarak Ali, Arun R, Saravanan S. Runtime partial reconfiguration of FPGAs for DSP applications[J]. Procedia Engineering, 2012,30:514-518.
[12]Rakan Khraisha, Jooheung Lee. A scalable H.264/AVC deblocking filter architecture using dynamic partial reconfiguration[C]// 2010 IEEE International Conference on Acoustics Speech and Signal Processing. 2010:1566-1569.
[13]Francisco Fons, Mariano Fons, Enrique Canto, et al. Real-time embedded systems powered by FPGA dynamic partial selfreconfiguration: A case study oriented to biometric recognition applications[J]. RealTime Image Processing, 2013,8(3):229-251.
[14]Bjrn Osterloh, Harald Michalik, Sandi Alexander Habinc. Dynamic partial reconfiguration in space applications[C]// NASA/ESA Conference on Adaptive Hardware and Systems. 2009:336-343.
[15]Katarina Paulsson, Michael Hübner, Jürgen Becker. Strategies to on-line failure recovery in self-adaptive systems based on dynamic and partial Reconfiguration[C]// NASA/ESA Conference on Adaptive Hardware and Systems. 2006:288-291.
[16]Neenu Joseph, Nirmal Kumar P. Power consumption reduction in a SDR based wireless communication system using partial reconfigurable FPGA[J]. International Journal of VLSI Design & Communication Systems, 2012,3(2):203-210.
[17]谭翔. 基于SCA架构的SOPC设计与实现[D]. 长沙:国防科技大学, 2011.
[18]Juan Valverde, Andres Otero, Miguel Lopez, et al. Using SRAM based FPGAs for power-aware high performance wireless sensor networks[J]. Sensors, 2012,12(3):2667-2692.
[19]Antonio De La Piedra, An Braeken, Abdellah Touhafi. Sensor systems based on FPGAs and their applications: A survey[J]. Sensors, 2012, 12(9):12235-12264.
[20]姚爱红,张国印,关琳. 基于动态可重构FPGA的自演化硬件概述[J]. 智能系统学报, 2008,3(5):436-442. |