Computer and Modernization ›› 2014, Vol. 0 ›› Issue (1): 211-213,218.

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Design and Implementation of Virtual Logic Analyzer Based on FPGA

  

  1. 1. College of Information Technology, Hebei University of Economics and Business, Shijiazhuang 050061, China;

     2. Research Dept., Hebei University of Economics and Business, Shijiazhuang 050061, China
  • Received:2013-07-30 Online:2014-01-20 Published:2014-02-10

Abstract: This paper introduces a virtual logic analyzer based on FPGA chip, which consists of signal conditioning circuit, sampling module, trigger module, communication module, NIOS Ⅱ soft-core, and bus interface. The 8-way parallel sampling is achieved. The sampling rate is up to 100MS/s.

Key words: parallel sampling, NIOS, signal conditioning circuit, sampling module, trigger module, communication module