[1] 张娟,张雪兰. 扩展的海明码及其在FLASH/EEPROM中的应用[J]. 兵工自动化, 2003,22(3):52-54.
[2] Chen Bainan, Zhang Xinmiao, Wang Zhongfeng. Error correction for multi-level NAND flash memory using Reed-Solomon codes[C]// Proceedings of the 2008 IEEE Workshop on Signal Processing Systems. 2008:94-99.
[3] 张文静,姚智慧. NAND Flash控制器中RS码的设计与验证[J]. 计算机工程与设计, 2013,34(7):2590-2594.
[4] Burton H. Inversionless decoding of binary BCH codes[J]. IEEE Transactions on Information Theory, 1971,17(4):464-466.
[5] 郭鹏,房亮,于沛玲. BCH编译码器在NAND Flash控制器中的应用研究[J]. 计算机技术与发展, 2014,24(1):179-183.
[6] Lee Y, Yoo H, Yoo I, et al. High-throughput and low-complexity BCH decoding architecture for solid-state drives[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014,22(5):1183-1187.
[7] 吴锋. 面向SSD控制器的LDPC编解码电路设计[D]. 南京:东南大学, 2013.
[8] 易旭,杜昊阳. LDPC码的研究进展和应用展望[J]. 通信技术, 2016,49(1):1-6.
[9] Haymaker K, Kelley C A. Structured bit-interleaved LDPC codes for MLC flash memory[J]. IEEE Journal on Selected Areas in Communications, 2014,32(5):870-879.
[10] Zaidi S A A, Awais M, Condo C, et al. FPGA accelerator of quasi cyclic EG-LDPC codes decoder for NAND flash memories[C]// Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing. 2013:190-195.
[11] Ho Kin-Chu, Chen Chih-Lung, Chang Hsie-Chia. A 520k (18900, 17010) array dispersion LDPC decoder architectures for NAND flash memory[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016,24(4):1293-1304.
[12] 沈佐兵. 固态硬盘设计中的关键技术研究[D]. 杭州:杭州电子科技大学, 2013.
[13] Regulapati V. Error Correction Codes in NAND Flash Memory[D]. The University of Texas at Austin, 2015.
[14] 辛杰锋. 闪速存储系统中纠错编码技术研究[D]. 西安:西安电子科技大学, 2013.
[15] 贺鹤云. LDPC码基础与应用[M]. 北京:人民邮电出版社, 2009.
[16] Micheloni R, Crippa L, Marelli A. Inside NAND Flash Memories[M]. Springer, 2010.
[17] Byeon D, Lee S, Lim Y, et al. A comparison between 63nm 8Gb and 90nm 4Gb multi-level cell NAND flash memory for mass storage application[C]// Proceedings of the 2005 IEEE Asian Solid-State Circuits Conference. 2005:13-16.
[19] Yoo H, Lee Y, Park I C. Area-efficient syndrome calculation for strong BCH decoding[J]. Electronics Letters, 2011,47(2):107-108.
[20] Choi Hyojin, Liu Wei, Sung Wonyong. VLSI implementation of BCH error correction for multilevel cell NAND flash memory[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2010,18(5):843-847.
[21] Cho Sung-gun, Ha J. Concatenated BCH codes for NAND flash memories[C]// Proceedings of the 2012 IEEE International Conference on Communications. 2012:2611-2616.
[22] Zhang Meng, Wu Fei, Xie Changsheng, et al. A novel optimization algorithm for Chien search of BCH codes in NAND flash memory devices[C]// Proceedings of the 2015 IEEE International Conference on Networking, Architecture and Storage. 2015:106-111.
[23] 任克强,吴帆,谢斌. 用于NAND Flash的长BCH编码快速算法[J]. 计算机应用研究, 2015,32(7):2027-2029.
[24] Lone F R, Puri A, Kumar S. Performance comparison of Reed Solomon code and BCH code over Rayleigh fading channel[J]. International Journal of Computer Applications, 2013,71(20):23-26.
[25] Gallager R. Low-density parity-check codes[J]. IRE Transactions on Information Theory, 1962,8(1):21-28.
[26] 宋顺. 基于LDPC的固态存储系统纠错编码技术研究[D]. 长沙:湖南大学, 2015.
[27] MacKay D J C, Neal R M. Near Shannon limit performance of low density parity check codes[J]. Electronics Letters, 1997,33(6): 457-458.
[28] Tanner R. A recursive approach to low complexity codes[J]. IEEE Transactions on Information Theory, 1981,27(5):533-547.
[29] Li Zongwang, Chen Lei, Zeng Lingqi, et al. Efficient encoding of quasi-cyclic low-density parity-check codes[J]. IEEE Transactions on Communications, 2006,54(1):71-81.
[30] Dai Yongmei, Yan Zhiyuan, Chen Ning. Optimal overlapped message passing decoding of quasi-cyclic LDPC codes[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2008,16(5):565-578.
[31] Chen Yanni, Parhi K K. Overlapped message passing for quasi-cyclic low-density parity check codes[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2004,51(6):1106-1113.
[32] Guilloud F, Boutillon E, Tousch J, et al. Generic description and synthesis of LDPC decoders[J]. IEEE Transactions on Communications, 2007,55(11):2084-2091.
[33] Paul B, Siddique A M, Islam R, et al. Performance analysis of low complexity error correcting codes[J]. International Journal of Computer Applications, 2012,59(14):1-4.
[34] Kim Jonghong, Cho Junho, Sung Wonyong. Error performance and decoder hardware comparison between EG-LDPC and BCH codes[C]// Proceedings of the 2010 IEEE Workshop on Signal Processing Systems. 2010:392-397. |