计算机与现代化 ›› 2012, Vol. 1 ›› Issue (11): 145-148+.doi: 10.3969/j.issn.1006-2475.2012.11.036
• 信息安全 • 上一篇 下一篇
殷伟凤
收稿日期:
修回日期:
出版日期:
发布日期:
YIN Wei-feng
Received:
Revised:
Online:
Published:
摘要： 针对目前广泛应用的低功耗低速嵌入式设备，以减少面积为目标，本文给出一个精简的实现AES加密算法的硬件结构。在字节置换模块的设计中，改进采用查找表的方法而只用组合逻辑实现，采用将GF(28)域中的元素映射为复合域GF(24)来求逆的方法，大量减少资源占用；对混合列计算进行优化设计；最后，采用Altera的Cyclone芯片基于VHDL语言实现AES加密算法，并给出仿真结果。
关键词: 对称块加密, Rijndael算法, 高级加密标准, 高斯域
Abstract: This paper presents a compact hardware architecture for the AES algorithm which aims at reducing hardware resources without using a memory. The architecture only requires one combined S-box for encryption, decryption and key expansion which implements the multiplicative inverse in the composite field GF(24). In addition, the optimized combined MixColumns module has a lower gate count than other designs that implement mix columns operation. VHDL code is developed for the implementation of 128-bit data encryption with Device Cyclone of Altera Family.
Key words: symmetric block cipher, Rijndael algorithm, advanced encryption standard, Gauss field
中图分类号:
TP309
TP368.1
殷伟凤. AES加密的资源优化设计及FPGA实现[J]. 计算机与现代化, 2012, 1(11): 145-148+.
YIN Wei-feng. Resource Optimization of Advanced Encryption Standard and Its Implementation for FPGA[J]. Computer and Modernization, 2012, 1(11): 145-148+.
0 / / 推荐
导出引用管理器 EndNote|Ris|BibTeX
链接本文: http://www.c-a-m.org.cn/CN/10.3969/j.issn.1006-2475.2012.11.036
http://www.c-a-m.org.cn/CN/Y2012/V1/I11/145
